1. Manage basic hardware resource through offering the hardware operation interface, realize file and directory management through file system API interface.

2. The compatibility and hardware resource requirement were discussed, and the theoretical upper limit of the efficiency was given.

3. Please consult the Hardware Resource List, Software Resource List, and Tariffs Guide for further details.

4. Through simplifying algorithm and optimizing circuit architecture[], hardware resource is decreased; circuit's area and power reduced.

5. The key problems such as selection of hardware resource, working routine, algorithm processing time, etc. are discussed in detail.

6. The hardware resource required for parallel Viterbi decoding shows an exponential increase with the increase of constraint length of convolutional code, which limits its hardware implementation.

7. In actual practice, hardware resource sharing and information resource sharing are often combined.

8. The key problems such as selection of hardware resource, working routine, video acquisition, software development, etc. are discussed in detail.

9. This design has the advantage of having a laconic structure and economizing the hardware resource.

10. Segment detection and dynamic suppress co-channel interference (CCI) are provided in the paper. It can largely reduce the complexity and hardware resource.

11. Mainly using interpretive mode, It rounded analysis and research majority function which need realized in decoding module, owing to finiteness of hardware resource in embedded system.

12. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration.

13. The simulation result shows that the multiplexer can integrate the functions of storing and multiplexing payload data flexibly with low rate of hardware resource utilization.

14. A way of remote data acquisition based on wire transmission network was studied and remote data acquisition by taking the advantage of internet hardware resource was realized in this paper.

15. The task data flow graph ( DFG ) was partitioned into several sub - modules under hardware resource constraint.

16. This scheme is easy to realize and has reduced the consumption of hardware resource.

17. The three parallel communication interfaces may be applied to extend the hardware resource of an application system.

18. We also introduce the development of device driver under QNX, include programme of the interrupt handler, management of hardware resource and interface between application and device driver.

19. The design of cooperation with software calculation and hardware operation saves the hardware resource and provides the update ability of the unknown cadences.

20. The new data process path in Baseband is constructed to optimize hardware resource when it is realized by the means of serial bit processing.