1. That command 15 the clock rate command .

2. In particular, they used a molecular clock rate derived from invertebrates, which is slower than the one based on vertebrates.

3. The relation between the synchronization of clock rate and the zeroth law of thermodynamics, and the relation between the singularity theorem and the third law of thermodynamics are pointed out.

4. CPU speed is influenced by several factors, including clock rate, word size, cache and instruction set size.

5. Their clock rate are continually improved and their embedded memory and peripherals grow fast, but the performance of the transfer between I/O channel and the memory is still poor.

6. Its superscalar capabilities are not aggressive, but a higher clock rate is expected.

7. A new synthesis method of baseband echo power spectrum, which adopts Direct Digital Synthesis (DDS) technology, reduces greatly the clock rate and data memory.

8. Data is transmitted out of the FIFO at a transmit clock rate using a transmit address pointer incremented at the transmit clock rate.

9. The number of stages completed each second is given by the so - called clock rate.

10. So they dropped the performance not only by reducing the clock rate, but also by truncating the L2 cache.

11. The results has shown, it is possible to get measurement precision of clock rate about 10-14 during the period of one month.

12. Some major puzzles in black hole theory and General Relativity, including Hawking radiation, information puzzle, singularity theorem and synchronization of clock rate, are presented.

13. With the zero-th law of thermodynamics equivalent to the transitivity of clock rate synchronization, the above-mentioned conclusion can also be obtained.

14. The synthesis results show this FFT structure can run at 52MHZ clock rate in XC4025E - 2. This FFT structure is easy to expand more points FFT structure.

15. An obvious solution is to use a processor with a faster clock rate,[http:///clock rate.html] but for any given technology there exists a physical limit where the clock simply can't go any faster.

16. One 1995 microprocessor uses this deeper pipeline to achieve a 300 - megahertz clock rate.

17. Overflow and underflow are averted by storing received data in a FIFO at different addresses using a receive address pointer incremented at a receive clock rate.

18. The method is a fully-digitized process at the sampling clock rate, so that it can be conveniently implemented by FPGA or DSP, whose synchronization precision can reach 1% of the sampling interval.

19. The results has shown, it is possible to get measurement precision of clock rate about 10-14 during the period...

20. One cause of bit slippage is overflow of a receive buffer that occurs when the transmitter's clock rate exceeds that of the receiver.

21. Because of the limits of feedback devices, high speed pseudo noise code generation cannot depend simply on the improvement of clock rate.